#ifndef __OB6710_H__
#define __OB6710_H__

/*  ========== BYTE Registers =============  */
sfr P0                   = 0x80;
sfr SP                   = 0x81;
sfr DPL                  = 0x82;
sfr DPH                  = 0x83;
sfr DPL1                 = 0x84;
sfr DPH1                 = 0x85;
sfr RCON                 = 0x86;
sfr PCON                 = 0x87;

sfr TCON                 = 0x88;
sfr TMOD                 = 0x89;
sfr TL0                  = 0x8A;
sfr TL1                  = 0x8B;
sfr TH0                  = 0x8C;
sfr TH1                  = 0x8D;
sfr TAKEY                = 0x8E;
sfr IFCON                = 0x8F;
// --------------------------------------------------------------------------
sfr P1                   = 0x90;
sfr AUX                  = 0x91;
sfr SRELL                = 0x92;
sfr SRELH                = 0x93;
sfr WDTC                 = 0x94;
sfr WDTK                 = 0x95;
sfr IRCON2               = 0x97;

sfr SCON                 = 0x98;
sfr SBUF                 = 0x99;
sfr IEN2                 = 0x9A;
sfr ISPFAL               = 0x9B;
sfr ISPFAH               = 0x9C;
sfr ISPFD                = 0x9D;
sfr ISPFC                = 0x9E;
// --------------------------------------------------------------------------
sfr P2                   = 0xA0;
sfr ADCC2                = 0xA2;
sfr ADCSC1               = 0xA3;
sfr ADCSC2               = 0xA4;
sfr ADCSC3               = 0xA5;
sfr ADCSC4               = 0xA6;
sfr ADCSL                = 0xA7;

sfr IEN0                 = 0xA8;
sfr IP0                  = 0xA9;
sfr ADCRS0L              = 0xAA;
sfr ADCRS0H              = 0xAB;
sfr ADCRS1L              = 0xAC;
sfr ADCRS1H              = 0xAD;
sfr ADCSH                = 0xAE;
sfr ADCCU                = 0xAF;
// --------------------------------------------------------------------------
sfr P3                   = 0xB0;
sfr ADC_UPDATE_DISABLE   = 0xB1;
sfr ADCRS2L              = 0xB2;
sfr ADCRS2H              = 0xB3;
sfr ADCRS3L              = 0xB4;
sfr ADCRS3H              = 0xB5;
sfr ADCINTEN             = 0xB6;
sfr ADCINTFlag           = 0xB7;

sfr IEN1                 = 0xB8;
sfr IP1                  = 0xB9;
sfr ADCCD                = 0xBA;
sfr ADCLATCON            = 0xBB;
sfr ADCTrigSource1       = 0xBC;
sfr ADCTrigSource2       = 0xBD;
sfr Timer1TrigADCL       = 0xBE;
sfr Timer1TrigADCH       = 0xBF;
// --------------------------------------------------------------------------
sfr IRCON                = 0xC0;
sfr CCEN                 = 0xC1;
sfr CCL1                 = 0xC2;
sfr CCH1                 = 0xC3;
sfr CCL2                 = 0xC4;
sfr CCH2                 = 0xC5;
sfr CCL3                 = 0xC6;
sfr CCH3                 = 0xC7;

sfr T2CON                = 0xC8;
sfr CCCON                = 0xC9;
sfr CRCL                 = 0xCA;
sfr CRCH                 = 0xCB;
sfr TL2                  = 0xCC;
sfr TH2                  = 0xCD;
sfr CCEN2                = 0xCE;
sfr CCUDBCNT             = 0xCF;
// --------------------------------------------------------------------------
sfr PSW                  = 0xD0;
sfr MD0                  = 0xD1;
sfr MD1                  = 0xD2;
sfr MD2                  = 0xD3;
sfr MD3                  = 0xD4;
sfr MD4                  = 0xE6;
sfr MD5                  = 0xEE;
sfr MDUCON               = 0xF6;
sfr ARCON                = 0xD5;
sfr PWMAUX               =0xD6;
sfr CCU_UPDATE_DISABLE   = 0xD7;

sfr INTDBCNT             = 0xD8;
sfr PWMOPMOD             = 0xD9;
sfr DUTY0L               = 0xDA;
sfr DUTY0H               = 0xDB;
sfr DUTY1L               = 0xDC;
sfr DUTY1H               = 0xDD;
sfr DUTY2L               = 0xDE;
sfr DUTY2H               = 0xDF;
// --------------------------------------------------------------------------
sfr ACC                  = 0xE0;
sfr FLTCONFIG            = 0xE1;
sfr FLTNF                = 0xE2;
sfr PWMPOLARITY          = 0xE3;
sfr OVRIDEDIS            = 0xE4;
sfr OVRIDEDATA           = 0xE5;
sfr ACMP1DBCNT           = 0xE6;
sfr ACMP1OUTPUT          = 0xE7;

sfr LVC                  = 0xE8;
sfr DEADTIME0            = 0xE9;
sfr PWMINTF              = 0xEA;
sfr PWMTBPOSTSCALE       = 0xEB;
sfr FLTPINDBCNT          = 0xEC;
sfr PWMSEV               = 0xED;
sfr ACMP2DBCNT           = 0xEE;
sfr OPACON               = 0xEF;
// --------------------------------------------------------------------------
sfr B                    = 0xF0;
sfr PERIODL              = 0xF1;
sfr PERIODH              = 0xF2;
sfr SEVTCMPL             = 0xF3;
sfr SEVTCMPH             = 0xF4;
sfr PWMEN                = 0xF5;
sfr ACMP0OUTPUT          = 0xF7;

sfr Delay4TransL         = 0xF8;
sfr Delay4TransH         = 0xF9;
sfr PWMTBC0              = 0xFA;
sfr PWMTBC1              = 0xFB;
sfr TBCOUNTERL           = 0xFC;
sfr TBCOUNTERH           = 0xFD;
sfr ACMP0CON             = 0xFE;
sfr ACMP1CON             = 0xFF;

#define ACMP2CON           (*((unsigned char volatile xdata*)0xFF5F))
#define ACMP2OUTPUT           (*((unsigned char volatile xdata*)0xFF5E))
// --------------------------------------------------------------------------
// for ADC Xdata(External data memory) addr;
#define ADCCAL           (*((unsigned char volatile xdata*)0xFFFF))
#define ADCSUM2_OFFSET   (*((unsigned char volatile xdata*)0xFFF7))
#define ADCSUM1_OFFSET   (*((unsigned char volatile xdata*)0xFFF6))
#define ADCSUM0_OFFSET   (*((unsigned char volatile xdata*)0xFFF5))
#define ADCSUM_RS        (*((unsigned char volatile xdata*)0xFFF4))
#define ADCSUM_CON       (*((unsigned char volatile xdata*)0xFFF3))
// --------------------------------------------------------------------------
// for GPIO Xdata(External data memory) addr;
#define P0M0             (*((unsigned char volatile xdata*)0xFFDF))
#define P0M1             (*((unsigned char volatile xdata*)0xFFDE))
#define P1M0             (*((unsigned char volatile xdata*)0xFFDD))
#define P1M1             (*((unsigned char volatile xdata*)0xFFDC))
#define P2M0             (*((unsigned char volatile xdata*)0xFFDB))
#define P2M1             (*((unsigned char volatile xdata*)0xFFDA))
#define P3M0             (*((unsigned char volatile xdata*)0xFFD9))
#define P3M1             (*((unsigned char volatile xdata*)0xFFD8))
#define P0BUFFEN         (*((unsigned char volatile xdata*)0xFFD7))
#define P1BUFFEN         (*((unsigned char volatile xdata*)0xFFD6))
#define P2BUFFEN         (*((unsigned char volatile xdata*)0xFFD5))
#define P3BUFFEN         (*((unsigned char volatile xdata*)0xFFD4))
#define IRIS             (*((unsigned char volatile xdata*)0xFFD3))
// --------------------------------------------------------------------------
// for TMPWM Xdata(External data memory) addr;
#define TMPWMC           (*((unsigned char volatile xdata*)0xFFBF))
#define TMPWMD0L         (*((unsigned char volatile xdata*)0xFFBE))
#define TMPWMD0H         (*((unsigned char volatile xdata*)0xFFBD))
#define TMPWMMDL         (*((unsigned char volatile xdata*)0xFFBC))
#define TMPWMMDH         (*((unsigned char volatile xdata*)0xFFBB))
// --------------------------------------------------------------------------
// for IIC Xdata(External data memory) addr;
#define IICCTL           (*((unsigned char volatile xdata*)0xFF9F))
#define IICS             (*((unsigned char volatile xdata*)0xFF9E))
#define IICA1            (*((unsigned char volatile xdata*)0xFF9D))
#define IICA2            (*((unsigned char volatile xdata*)0xFF9C))
#define IICRWD           (*((unsigned char volatile xdata*)0xFF9B))
#define IICEBT           (*((unsigned char volatile xdata*)0xFF9A))
// --------------------------------------------------------------------------
// for DAC;
#define DACVAL1          (*((unsigned char volatile xdata*)0xFF7F))
#define DACVAL0          (*((unsigned char volatile xdata*)0xFF7E))
#define DACCON           (*((unsigned char volatile xdata*)0xFF7C))
// --------------------------------------------------------------------------
// for ACMP;
#define ACMP2CON         (*((unsigned char volatile xdata*)0xFF5F))	
#define ACMP2OUTPUT      (*((unsigned char volatile xdata*)0xFF5E))	
#define ACMP2DBCNT       (*((unsigned char volatile xdata*)0xFF5D))	
#define ACMP1DBCNT       (*((unsigned char volatile xdata*)0xFF5C))	
#define ACMP0DBCNT       (*((unsigned char volatile xdata*)0xFF5B))	
#define ACMPHYS          (*((unsigned char volatile xdata*)0xFF5A))	
// --------------------------------------------------------------------------
// for PWM;
#define MODE_5           (*((unsigned char volatile xdata*)0xFF4F))
#define OVRDAT_5         (*((unsigned char volatile xdata*)0xFF4E))
#define OVRDIS_5         (*((unsigned char volatile xdata*)0xFF4D))
#define OCS2_5           (*((unsigned char volatile xdata*)0xFF4C))
#define OCS1_5           (*((unsigned char volatile xdata*)0xFF4B))
#define OCS0_5           (*((unsigned char volatile xdata*)0xFF4A))
#define MODE_4           (*((unsigned char volatile xdata*)0xFF49))
#define OVRDAT_4         (*((unsigned char volatile xdata*)0xFF48))
#define OVRDIS_4         (*((unsigned char volatile xdata*)0xFF47))
#define OCS2_4           (*((unsigned char volatile xdata*)0xFF46))
#define OCS1_4           (*((unsigned char volatile xdata*)0xFF45))
#define OCS0_4           (*((unsigned char volatile xdata*)0xFF44))
#define MODE_3           (*((unsigned char volatile xdata*)0xFF43))
#define OVRDAT_3         (*((unsigned char volatile xdata*)0xFF42))
#define OVRDIS_3         (*((unsigned char volatile xdata*)0xFF41))
#define OCS2_3           (*((unsigned char volatile xdata*)0xFF40))
#define OCS1_3           (*((unsigned char volatile xdata*)0xFF3F))
#define OCS0_3           (*((unsigned char volatile xdata*)0xFF3E))
#define MODE_2           (*((unsigned char volatile xdata*)0xFF3D))
#define OVRDAT_2         (*((unsigned char volatile xdata*)0xFF3C))
#define OVRDIS_2         (*((unsigned char volatile xdata*)0xFF3B))
#define OCS2_2           (*((unsigned char volatile xdata*)0xFF3A))
#define OCS1_2           (*((unsigned char volatile xdata*)0xFF39))
#define OCS0_2           (*((unsigned char volatile xdata*)0xFF38))
#define MODE_1           (*((unsigned char volatile xdata*)0xFF37))
#define OVRDAT_1         (*((unsigned char volatile xdata*)0xFF36))
#define OVRDIS_1         (*((unsigned char volatile xdata*)0xFF35))
#define OCS2_1           (*((unsigned char volatile xdata*)0xFF34))
#define OCS1_1           (*((unsigned char volatile xdata*)0xFF33))
#define OCS0_1           (*((unsigned char volatile xdata*)0xFF32))
#define MODE_0           (*((unsigned char volatile xdata*)0xFF31))
#define OVRDAT_0         (*((unsigned char volatile xdata*)0xFF30))
#define OVRDIS_0         (*((unsigned char volatile xdata*)0xFF2F))
#define OCS2_0           (*((unsigned char volatile xdata*)0xFF2E))
#define OCS1_0           (*((unsigned char volatile xdata*)0xFF2D))
#define OCS0_0           (*((unsigned char volatile xdata*)0xFF2C))
#define HALLSEL          (*((unsigned char volatile xdata*)0xFF2B))
#define HALLCON          (*((unsigned char volatile xdata*)0xFF2A))
#define DISFUPL          (*((unsigned char volatile xdata*)0xFF27))
#define DISFUPH          (*((unsigned char volatile xdata*)0xFF26))
#define DISFDNL          (*((unsigned char volatile xdata*)0xFF25))
#define DISFDNH          (*((unsigned char volatile xdata*)0xFF24))
#define OCS2             (*((unsigned char volatile xdata*)0xFF23))
#define OCS1             (*((unsigned char volatile xdata*)0xFF22))
#define OCS0             (*((unsigned char volatile xdata*)0xFF21))
#define DISCON           (*((unsigned char volatile xdata*)0xFF20))
// --------------------------------------------------------------------------
// for PI;
#define PICON            (*((unsigned char volatile xdata*)0xFF10))
#define PIINL            (*((unsigned char volatile xdata*)0xFF0F))
#define PIINH            (*((unsigned char volatile xdata*)0xFF0E))
#define PIPARLL          (*((unsigned char volatile xdata*)0xFF0D))
#define PIPARLH          (*((unsigned char volatile xdata*)0xFF0C))
#define PIPARHL          (*((unsigned char volatile xdata*)0xFF0B))

#define PIOUTL           (*((unsigned char volatile xdata*)0xFF09))
#define PIOUTH           (*((unsigned char volatile xdata*)0xFF08))
#define PILMTLL          (*((unsigned char volatile xdata*)0xFF07))
#define PILMTLH          (*((unsigned char volatile xdata*)0xFF06))
#define PILMTHL          (*((unsigned char volatile xdata*)0xFF05))	

#define PITARL           (*((unsigned char volatile xdata*)0xFF03))	
#define PITARH           (*((unsigned char volatile xdata*)0xFF02))	
#define PIKI             (*((unsigned char volatile xdata*)0xFF01))	
#define PIKP             (*((unsigned char volatile xdata*)0xFF00))	
// --------------------------------------------------------------------------
// for Timer3;
#define TL3            (*((unsigned char volatile xdata*)0xFEFF))
#define TH3            (*((unsigned char volatile xdata*)0xFEFE))
#define T3CNTL         (*((unsigned char volatile xdata*)0xFEFD))
#define T3CNTH         (*((unsigned char volatile xdata*)0xFEFC))
#define T3NDIV         (*((unsigned char volatile xdata*)0xFEFB))
#define T3CON          (*((unsigned char volatile xdata*)0xFEFA))
// --------------------------------------------------------------------------
// for Misc Xdata(External data memory) addr;
#define RSTS             (*((unsigned char volatile xdata*)0xFEDF))
#define SWRES            (*((unsigned char volatile xdata*)0xFEDE))
#define ENHIT            (*((unsigned char volatile xdata*)0xFEDD))
#define PFCON            (*((unsigned char volatile xdata*)0xFEDC))
// --------------------------------------------------------------------------
#define REMAP            (*((unsigned char volatile xdata*)0xFEC8))
// --------------------------------------------------------------------------

// for Check Sum;
#define CSRSLL           (*((unsigned char volatile xdata*)0xFEBF))
#define CSRSLH           (*((unsigned char volatile xdata*)0xFEBE))
#define CSRSHL           (*((unsigned char volatile xdata*)0xFEBD))	
#define CSRSHH           (*((unsigned char volatile xdata*)0xFEBC))	
#define CSCON            (*((unsigned char volatile xdata*)0xFEBB))	
#define CSDISEND         (*((unsigned char volatile xdata*)0xFEBA))	
#define CSDISSTART       (*((unsigned char volatile xdata*)0xFEB9))	


#define gFC00            (*((unsigned char volatile xdata*)0xFC00))	
#define gFC01            (*((unsigned char volatile xdata*)0xFC01))	
#define gFC02            (*((unsigned char volatile xdata*)0xFC02))	
#define gFC03            (*((unsigned char volatile xdata*)0xFC03))	
#define gFC04            (*((unsigned char volatile xdata*)0xFC04))	
#define gFC09            (*((unsigned char volatile xdata*)0xFC09))	

/*  ========== BIT Registers =============  */
/* sfr TCON              = 0x88; */
sbit TF1      = TCON^7;
sbit TR1      = TCON^6;
sbit TF0      = TCON^5;
sbit TR0      = TCON^4;
sbit IE1      = TCON^3;
sbit IT1      = TCON^2;
sbit IE0      = TCON^1;
sbit IT0      = TCON^0;

/* sfr SCON             = 0x98; */
sbit SM0      = SCON^7;
sbit SM1      = SCON^6;
sbit SM20     = SCON^5;
sbit REN0     = SCON^4;
sbit TB80     = SCON^3;
sbit RB80     = SCON^2;
sbit TI0      = SCON^1;
sbit RI0      = SCON^0;

/* sfr IEN0              = 0xA8; */
sbit EA       = IEN0^7;
sbit ET2      = IEN0^5;
sbit ES0      = IEN0^4;
sbit ET1      = IEN0^3;
sbit ET0      = IEN0^1;
sbit EX0      = IEN0^0;

/* sfr IEN1              = 0xB8; */
sbit IEIIC    = IEN1^5;
sbit IELVI    = IEN1^4;
sbit IEACMP2  = IEN1^3;
sbit IEADC    = IEN1^2;

/* sfr IRCON             = 0xC0; */
sbit EXF2	    = IRCON^7;
sbit TF2      = IRCON^6;
sbit IICIF    = IRCON^5;
sbit LVIIF    = IRCON^4;
sbit ACMP2IF  = IRCON^3;
sbit ADCIF    = IRCON^2;
sbit PWMIF    = IRCON^0;
/* sfr PSW               = 0xD0;  */
sbit CY       = PSW^7;
sbit AC       = PSW^6;
sbit F0       = PSW^5;
sbit RS1      = PSW^4;
sbit RS0      = PSW^3;
sbit OV       = PSW^2;
sbit P        = PSW^0;   //8052 only

/* sfr P0                = 0x80;*/
sbit P0_0      = P0^0;
sbit P0_1      = P0^1;
sbit P0_2      = P0^2;
sbit P0_3      = P0^3;
sbit P0_4      = P0^4;
sbit P0_5      = P0^5;
sbit P0_6      = P0^6;
sbit P0_7      = P0^7;

/* sfr P1                = 0x90;*/
sbit P1_0      = P1^0;
sbit P1_1      = P1^1;
sbit P1_2      = P1^2;
sbit P1_3      = P1^3;
sbit P1_4      = P1^4;
sbit P1_5      = P1^5;
sbit P1_6      = P1^6;

/* sfr P2                = 0xA0;*/
sbit P2_0      = P2^0;
sbit P2_1      = P2^1;
sbit P2_2      = P2^2;
sbit P2_3      = P2^3;
sbit P2_4      = P2^4;
sbit P2_5      = P2^5;
sbit P2_6      = P2^6;
sbit P2_7      = P2^7;

/* sfr P3                = 0xB0;*/
sbit P3_0      = P3^0;
sbit P3_1      = P3^1;
sbit P3_2      = P3^2;
sbit P3_3      = P3^3;
sbit P3_4      = P3^4;
sbit P3_5      = P3^5;
sbit P3_6      = P3^6;


/*  Interrupt Define  */
#define d_INT0_Vector           0    //0003h
#define d_T0_Vector             1    //000Bh
#define d_T1_Vector             3    //001Bh
#define d_UART0_Vector          4    //0023h
#define d_T2_Vector             5    //002Bh
#define d_T3_Vector             6    //0033h
#define d_ACMP1_Vector          7   //005Bh
#define d_PWM_Vector            8    //0043h
#define d_ADC_Vector            10   //0053h
#define d_ACMP2_Vector          11   //005Bh
#define d_LVI_Vector            12   //0063h
#define d_IIC_Vector            13   //006Bh
#define d_WDT_Vector            17   //008Bh
#define d_ACMP0_Vector          18   //0093h

#endif

